The past few years have experienced spectacular advances in the fabrication and manipulation of new nanoscale switching devices. Although new nanoscale switching devices show significant future promise, there is a growing consensus that, at least in the near term, they cannot completely replace CMOS technology. As a result, there is a substantial demand to explore the opportunities for nanoscale CMOS and emerging non-silicon devices to enhance and complement each other to sustain the Moore's Law beyond the CMOS scaling limits. Accordingly, hybrid CMOS/nanodevice circuits are being explored. A conceptual schematic of the principle structure of a hybrid CMOS/nanodevice circuit is illustrated in FIG. 1, where an array of nanoscale wire (“nanowire”) crossbars 10 sits on the top of a CMOS circuit 20. Referring to the inset of FIG. 1, the nanowire crossbars of the array 10 include a first layer of nanowires 11 arranged in a first direction and a second layer of nanowires 12 arranged in a second direction. The nanowires 11 of the first layer and the nanowires of the second layer 12 are connected by simple nanodevices 15 at each crosspoint. The crosspoint nanodevices 15 are responsible for the bulk of information processing and/or storage, while the CMOS circuit 20 performs signal restoration, testing, I/O, global interconnect, and other functions. Such a combination leverages the density and low cost advantages of nanodevices and allows the functionality, flexibility, and reliability of CMOS circuits to be used to its fullest extent.
One of the main design issues in hybrid nanoelectronic circuits is the interface between highly dense nanowires within nanodevice crossbars and photolithographically defined features of the CMOS subsystem (“microwires”). Several possible solutions have been proposed to tackle this challenge, which may be categorized based on whether the microwire-to-nanowire accessibility is realized through direct microwire-nanowire ohmic contact or a logic circuit called a microwire-to-nanowire demultiplexer (demux). The current demux design solutions have a crossbar structure consisting of one layer of parallel nanowires and one layer of parallel microwires (see e.g., FIG. 2). A demux takes the voltages of all the microwires as input to drive the voltage of only one nanowire (the selected nanowire) to a pre-specified value. Meanwhile, in order to ensure good operation reliability, the demux should keep the voltages of all the unselected nanowires well constrained in a safety window far away from that of the selected nanowire or keep all the unselected nanowires floating. In prior work on demux design, such demultiplexing function is realized by implementing a single type of device such as a resistor, a diode, or a field effect transistor (FET) at a subset of the microwire-nanowire crosspoints. Because the nonlinear nature of a diode's and FET's electrical characteristics can well match the nonlinear nature of the desired demultiplexing function, diode-logic and FET-logic demuxes can, in principle, very well approximate the ideal demultiplexing behavior. However, as pointed out in “Resistor-Logic Demultiplexers for Nanoelectronics Based on Constant-Weight Codes” by Kuekes et al. (Nanotechnology, vol. 17, pp. 1052-61, 2006) and “Crossbar Demultiplexers for Nanoelectronics Based on N-Hot Codes” by Snider et al. (IEEE Trans. on Nanotech., vol. 4, pp. 249-54, 2005), which are herein incorporated by reference in their entirety, diode-logic and FET-logic demuxes suffer from significant difficulties of reliable fabrication using current technology. Moreover, FET-logic demuxes tend to suffer from low operational speed because of the serial chains of FETs along the signal path. In contrast, these issues may be much less serious for a resistor-logic demux. Nevertheless, due to the linear nature of a resistor's electrical characteristics, a resistor-logic demux inherently cannot well approximate the desired nonlinear demultiplexing behavior. Recent work by Kuekes et al. and Snider et al. above has applied constant weight codes, a topic in classical coding theory, to design a resistor-logic demux structure with optimal operation margin, which may relatively better approximate the demultiplexing behavior.
As illustrated in FIG. 2, a resistor-logic demux typically has a microwire-nanowire crossbar structure (101/201) with identical resistors 50 implemented at certain microwire-nanowire crosspoints. Let Nmicro and Nnano denote the number of microwires and nanowires within the resistor-logic demux crossbar, respectively. All the resistors at the crosspoints form Nnano distinct resistor-based linear voltage dividers that share the same Nmicro input voltages, and each voltage divider drives one individual nanowire. If a ‘1’ and a ‘0’ are used to represent the presence and absence, respectively, of a resistor at each crosspoint, each nanowire (and hence each voltage divider) can be represented by an Nmicro-bit nanowire characteristic vector. Accordingly, the entire demux can be represented by an Nnano×Nmicro demux characteristic matrix in which each row is one nanowire characteristic vector, as illustrated in FIG. 2. For example, for the resistor-logic demux of FIG. 2, the top row is represented by the nanowire characteristic vector [1 1 0 0] where a resistor 50 is present at the first two crosspoints in the row and a resistor is absent at the second two crosspoints in the row. The next row is represented by the nanowire characteristic vector [1 0 1 0] where a resistor 50 is present at the first and third crosspoints and a resistor is absent at the second and fourth crosspoints. Similarly, the third row is represented by the nanowire characteristic vector [1 0 0 1] where a resistor 50 is present at the first and fourth crosspoints and a resistor is absent at the second and third crosspoints.
As described above, a demux should drive the voltage of only one nanowire (i.e., the selected nanowire) to a pre-specified value and keep the voltages of all the unselected nanowires well constrained in a safety window far away from that of the selected nanowire or keep all the unselected nanowires floating. Let Vsel denote the desired output voltage of the selected nanowire. It can be assumed that the input voltage on each microwire can be either Vsel or V0, and an Nmicro-bit input vector can be defined in which ‘1’ and ‘0’ represent that the voltage of the corresponding microwire is to be Vsel and V0, respectively. Hence, the input vector of the microwires is set equal to the characteristic vector of the nanowire to be selected. Given one binary vector s, let wt(s) denote its Hamming weight (i.e., the number of 1's in the binary vector s). Given the input vector h, the output voltage of the nanowire with the characteristic vector v is
                                                        wt              ⁡                              (                                  h                  ⁢                                                                          ⁢                  AND                  ⁢                                                                          ⁢                  v                                )                                                    wt              ⁡                              (                v                )                                              ·                      (                                          V                set                            -                              V                0                                      )                          +                              V            0                    .                                    (        1        )            
Let Vwirem denote the minimum value of the voltage differences between the selected nanowire and any unselected nanowires. In general, the objective of resistor-logic demux design is to maximize Vwirem/Vsel in order to improve the operational reliability. However, in the context of crossbar nanoelectronic circuits that are of most practical interest, the objective of resistor-logic demux design is beyond mere maximization of Vwirem/Vsel. For crossbar nanoelectronic circuits, a pair of demuxes is used to drive both the rows and the columns of nanowires. The crosspoint of the selected row nanowire (see reference 11 of FIG. 1) and the selected column nanowire (see reference 12 of FIG. 1) is where the selected nanodevice (see reference 15 of FIG. 1) under operation lies. The magnitude of the voltage drop across the selected nanodevice under operation, denoted as ΔVsel, typically should be greater than that of any other unselected nanodevices. Let Δνunsel denote the set of the magnitudes of voltage drops across any unselected nanodevices. In this context, the main objective of demux design is to maximize νm (i.e., the normalized margin of the voltages across the selected and unselected nanodevices), which is defined as
                              v          m                =                  1          -                                                    max                ⁡                                  (                                      Δ                    ⁢                                                                                  ⁢                                          v                      unsel                                                        )                                                            Δ                ⁢                                                                  ⁢                                  V                  sel                                                      .                                              (        2        )            
Mere maximization of Vwirem/Vsel for the individual row or column resistor-logic demux does not necessarily maximize the normalized margin νm. Since how to design the demux (i.e., how to construct the demux characteristic matrix) to only maximize Vwirem/Vsel is already nontrivial, the design of optimum row and column demuxes for nanodevice crossbars certainly becomes more challenging.
It has been well demonstrated by Kuekes et al. and Snider et al. above that constant weight codes can be readily leveraged to tackle this challenge. Since only binary constant weight code is used in this context, the term constant weight code within this disclosure refers to binary constant weight code. The constant weight code is a code where all codewords have the same Hamming weight. A constant weight code is denoted as (n, M, dmin, dmax, w), where n is the length of each codeword, M is the number of codewords, dmin and dmax are the minimum and maximum Hamming distance between any two codewords, and w is the weight of the codewords. To design a resistor-logic demux with Nmicro microwires and Nnano nanowires, a constant weight code is constructed as (Nmicro, Nnano, dmin, dmax, w) and each Nmicro-bit codeword is assigned as one nanowire characteristic vector. For any two codewords s and t in a constant weight code, wt(s AND t)=w−dist(s,t)/2, where dist(s,t) denotes the Hamming distance between s and t. Therefore, equation (1) can be rewritten as
                                                        w              -                                                dist                  ⁡                                      (                                          h                      ,                      v                                        )                                                  /                2                                      w                    ·                      (                                          V                sel                            -                              V                0                                      )                          +                  V          0                                    (        3        )            
With the assumption that the row and column demuxes are identical (i.e., they use the same constant weight code), it has been shown by Kuekes et al. above that the normalized voltage margin νm defined in equation (2) is equal to 2dmin/(2dmax+dmin). Therefore, in order to maximize the normalized margin νm, the ratio dmin/dmax should be maximized. In addition, it is clear from equation (3) that the maximization of Vwirem/Vsel for each demux only requires to maximize dmin. Meanwhile, it is desirable for the row and column demuxes to use as few numbers of microwires as possible in order to reduce the area overhead. Therefore, for nanodevice crossbar circuits with Nnano nanowires along each direction, the essential demux design challenge is how to construct a constant weight code (Nmicro, Nnano, dmin, dmax, w) that has a minimum value of Nmicro and maximum value of dmin/dmax. However, minimization of Nmicro and maximization of dmin/dmax are typically conflicting to each other. That is, in order to increase the ratio dmin/dmax, a constant weight code with longer codeword length (or the value of Nmicro) may have to be used. As shown in “Resistor-Logic Demultiplexers for Nanoelectronics Based on Constant-Weight Codes” by Kuekes et al., a constant weight code (8, 70, 2, 8, 4) can drive 70 nanowires using 8 microwires and has the ratio dmin/dmax=¼. In order to increase the ratio dmin/dmax from ¼ to ⅔, a constant weight code (19, 70, 8, 12, 9) that requires 19 input microwires must be used.
Thus, there exists a need in the art for an improved demultiplexer design and system.